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EMPLOYMENT

[Vietnam] SoC Backend Implementation Engineer

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작성일 21-11-26 09:00

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I. GENERAL INFORMATION/ THÔNG TIN CHUNG

1

Job title

SoC Backend Implementation Engineer

2

Type

Full time

3

Rank

Senior

4

Group

Design Service

5

Department

Design Centre

6

Superior’s title

Senior Manager

 

 

 

II. PURPOSE OF THE JOB/ MỤC ĐÍCH CÔNG VIỆC

Responsible for all aspects of the SoC physical design flow including but not limited to: floor-planning, place and route, timing and power, physical verification, and full chip design database ready for manufacturing.

 

III. MAIN FUNCTIONS/ CHỨC NĂNG CHÍNH

1

Work with the FE team to understand chip architecture and dependencies between different domains then drive physical aspects early in design cycle.

2

Responsible for full chip physical design both flat and hierarchical.

3

Create full chip floor plan including pin placement, partitions and power grid.

4

Develop and validate high performance low power clock network guidelines.

5

Perform block level place, route and close the design to meet timing, area and power constraints.

6

Generate and implement ECOs to fix timing, noise and EM IR violations.

7

Run Physical design verification flow at chip/block level and come up with guidelines and checklist, execute and track progress.

8

Work with expert team to identify potential solution, drive execution and improvement in PD work methodologies.

9

Manage, assist, and resolve technical issues related to PD work with team members.

10

Work with counterparts in other sites to jointly execute projects as an integral part of the team in global environment.

11

Support project managers with effort estimations and resource planning.

12

Support team leader in coaching, training and development team members.

 

 

IV. RECRUITMENT REQUIREMENTS/ TIÊU CHUẨN TUYỂN DỤNG TỐI THIỂU

1

Education Required

University and above

2

Major

Electrical and Electronics, Computer science

3

Experience

At least 5 years of experience in Physical Design

4

Job related requirements

Experience in low power/multi voltage design and understanding of UPF.

Worked on multiple tape-outs at ultra-deep sub-micron technologies, 28nm and smaller nodes, in complex multi-million gate designs.

Deep knowledge of Synopsys or Cadence implementation tools and flow.

Have hands on experience in completing RTL to GDSII flow, which includes synthesis, DFT, IO planning, floor-planning, power analysis, P&R, CTS, extraction, timing closure, physical verification, rail analysis etc.,

Strong technical knowledge in microelectronics and/or system architectures.

Knowledge on package design, ESD, integration of analog and mixed signal macros.

Excellent debugging skills for design issues.

Experience in using Perl and TCL/TK to achieve highly automated, reproducible and fast results.

5

Other requirements

Good communication and interpersonal skills.

Good at English

Logical thinking

Research and apply new technology

Analytic and troubleshoot problem/

Careful

Ability to multi-task and can work under deadline pressure.

6

Age

28+

7

Gender

Male - Female

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