TOP


EMPLOYMENT

EMPLOYMENT

[Vietnam] RTL Design Engineer

페이지 정보

작성일 21-11-26 08:51

본문

I. GENERAL INFORMATION/ THÔNG TIN CHUNG

1

Job title

RTL Design Engineer

2

Type

Full time

3

Rank

Senior

4

Group

Design Service

5

Department

Design Centre

6

Superior’s title

Senior Manager

 

 

 

II. PURPOSE OF THE JOB/ MỤC ĐÍCH CÔNG VIỆC

Responsible for RTL engineer from concept study, architecture definition, design and verification, to silicon bring-up and characterization.

 

III. MAIN FUNCTIONS/ CHỨC NĂNG CHÍNH

Roles & Responsibilities

§ Study the requirements of the digital functions then describe the logic functionalities of the design in form block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts.

§ Implement RTL in Verilog/SystemVerilog, perform unit level testing, debug tests, SDC and UFP generation.   

§ Perform RTL Lint check, RTL synthesis, Equivalence checking, CDC checking and support Static Timing Analysis.

§ Make sure designs are delivered on time and with the highest quality by using proper checks.

§ Resolve technical issues in developing digital blocks, gate level simulation, power and static timing analysis with team members.

§ Work with verification team for test plan/strategy to meet all functional requirements and performance

§ Work with timing and physical team for timing closure and meet power and area goals

§ Support project managers with effort estimations and resource planning

§ Support team leader in coaching, training and development team members.

 

 

IV. RECRUITMENT REQUIREMENTS/ YÊU CẦU

1

Education Required

University and higher

2

Major

Electrical and Electronics, Computer science or related majors

3

Experience

5+ years experienced in digital circuit design.

4

Job related requirements

-   Good experience in digital design flow including: RTL coding, RTL simulation, logic synthesis, timing constraints, timing closure, STA, gate level simulation and equivalence checking.

-   Very skilled in Hardware Description Languages: Verilog and SystemVerilog.

-   Familiar with JIRA project management system and git control system.

5

Other requirements

Good communication skills in English and have excellent interpersonal communication skills and ability to work in large international teams.

Logical thinking

Research and apply new technology

Analytic and troubleshoot problem/

Careful

Ability to multi-task and can work under deadline pressure.

6

Gender

Male - Female


Pls contact HR Dept:      HOTLINE – 0962.42.1919             EMAIL: doan.tran@coasia.com

 

첨부파일