I. GENERAL INFORMATION/ THÔNG TIN CHUNG

1

Job title

SoC Backend Implementation Engineer

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Type

Full time

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Rank

Senior

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Group

Design Service

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Department

Design Centre

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Superior’s title

Senior Manager

II. PURPOSE OF THE JOB/ MỤC ĐÍCH CÔNG VIỆC

Responsible for all aspects of the SoC physical design flow including but not limited to: floor-planning, place and route, timing and power, physical verification, and full chip design database ready for manufacturing.

III. MAIN FUNCTIONS/ CHỨC NĂNG CHÍNH

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Work with the FE team to understand chip architecture and dependencies between different domains then drive physical aspects early in design cycle.

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Responsible for full chip physical design both flat and hierarchical.

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Create full chip floor plan including pin placement, partitions and power grid.

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Develop and validate high performance low power clock network guidelines.

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Perform block level place, route and close the design to meet timing, area and power constraints.

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Generate and implement ECOs to fix timing, noise and EM IR violations.

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Run Physical design verification flow at chip/block level and come up with guidelines and checklist, execute and track progress.

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Work with expert team to identify potential solution, drive execution and improvement in PD work methodologies.

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Manage, assist, and resolve technical issues related to PD work with team members.

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Work with counterparts in other sites to jointly execute projects as an integral part of the team in global environment.

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Support project managers with effort estimations and resource planning.

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Support team leader in coaching, training and development team members.

IV. RECRUITMENT REQUIREMENTS/ TIÊU CHUẨN TUYỂN DỤNG TỐI THIỂU

1

Education Required

University and above

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Major

Electrical and Electronics, Computer science

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Experience

At least 5 years of experience in Physical Design

4

Job related requirements

Experience in low power/multi voltage design and understanding of UPF.

Worked on multiple tape-outs at ultra-deep sub-micron technologies, 28nm and smaller nodes, in complex multi-million gate designs.

Deep knowledge of Synopsys or Cadence implementation tools and flow.

Have hands on experience in completing RTL to GDSII flow, which includes synthesis, DFT, IO planning, floor-planning, power analysis, P&R, CTS, extraction, timing closure, physical verification, rail analysis etc.,

Strong technical knowledge in microelectronics and/or system architectures.

Knowledge on package design, ESD, integration of analog and mixed signal macros.

Excellent debugging skills for design issues.

Experience in using Perl and TCL/TK to achieve highly automated, reproducible and fast results.

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Other requirements

Good communication and interpersonal skills.

Good at English

Logical thinking

Research and apply new technology

Analytic and troubleshoot problem/

Careful

Ability to multi-task and can work under deadline pressure.

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Age

28+

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Gender

Male - Female