I. GENERAL INFORMATION/ THÔNG TIN CHUNG

1

Job title

SoC Frontend Implementation Engineer

2

Type

Full time

3

Rank

Senior

4

Group

Design Service

5

Department

Design Centre

6

Superior’s title

Senior Manager

II. PURPOSE OF THE JOB/ MỤC ĐÍCH CÔNG VIỆC

Perform all frontend implementation related works including but not limited to: netlist synthesis, DFT implementation &Test vector generation, formal verification, and static timing analysis.

III. MAIN FUNCTIONS/ CHỨC NĂNG CHÍNH

1

Develop and verify timing constraints based on the design specification; and build the synthesis environment to synthesize digital, mix-signal chips in advanced process nodes.

2

Derive timing signoff factors to check the design timing with MCMM (multi corners multi modes).

3

Work with RTL design engineers to perform STA at a large million gates design; to detect mismatch issues in RTL, build the constraint, optimize the circuit, and analyze timing; to optimize and determine the critical paths; and to provide the suggestion to RTL design engineers.

4

Support to RTL design engineers in running Formality on ECO netlist; debug mismatched errors of the ECO netlist; and debug timing violations.

5

Work with layout engineers to isolate and identify the worst placement; to choose an optimized cell layout structure; and support the timing report, ECO fixing.

6

Support DFT engineers to implement DFT test flow including scan insertion, MBIST, scan compress/decompress for pin limited design, etc. 

7

Develop working methodologies which includes RTL synthesis flow, DFT insertion flow and low power synthesis flow by using industry standard EDA tools. 

8

Use ASICs CAD support for multi-VDD designs and make use the benefits of the power-intent designs using UPF.

11

Support project managers with effort estimations and resource planning.

12

Support team leader in coaching, training and development team members.

IV. RECRUITMENT REQUIREMENTS/ TIÊU CHUẨN TUYỂN DỤNG TỐI THIỂU

1

Education Required

University and above

2

Major

Electrical and Electronics, Computer science

3

Experience

At least 5 years of experience in RTL synthesis, STA, DFT, Power Analysis etc.

4

Job related requirements

Experience in multiple clocks designs and low power design such as: Dynamic power optimization, MultiVt optimization, Clock gating, Dynamic and Adaptive Voltage Frequency Scaling.

Excellent in manipulate primetime TCL script to generate timing report for a large design.

Deep knowledge of: synthesis, timing, equivalent checks, RC-extraction, noise, power, UPF, etc.

Experienced in using EDA tools such as: Design Compiler, Power Compiler, Formality, Primetime, Design For Test, TetraMax, etc.

Good knowledge in Design For Test implementation.

5

Other requirements

Good communication and interpersonal skills.

Good at English

Logical thinking

Research and apply new technology

Analytic and troubleshoot problem

Careful

Ability to multi-task and can work under deadline pressure.

6

Age

28+

7

Gender

Male - Female