I. GENERAL INFORMATION/ THÔNG TIN CHUNG

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Job title

RTL Design Leader (Manager)

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Type

Full time

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Rank

Manager

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Group

Design Service

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Department

Design Centre

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Superior’s title

Senior Manager

II. PURPOSE OF THE JOB/ MỤC ĐÍCH CÔNG VIỆC

Responsible for RTL Leader level from concept study, architecture definition, design and verification, to silicon bring-up and characterization.

III. MAIN FUNCTIONS/ CHỨC NĂNG CHÍNH

Roles & Responsibilities

§  Develop the microarchitecture specification based on advanced design techniques of Clock/Voltage domain crossing, DFT and Low Power Design.

§  Perform TOP level integration, STA and low-power design (UPF) for AP SOC which includes CPU higher than Cortex-A53, GPU, USB3, Ethernet, MIPI, PCIe and LPDDR4/5.

§  Develop RTL for both block level and top level integration which includes SDC, UPF, Lint, CDC, DFT-coverage, DFT mux / GPIO, Ballmap, PAD sequence, etc. based on design spec and coding guidelines.

§  IP design will focus on IP itself, configuration, link & PHY integration, IP level simulation, subsystem level simulation, IP or subsystem level SDC, UPF and basic functional simulation. And hand out those IPs to Chip Integration Design team.

§  Develop functional test-benched to ensure behavior and performance of the design.

§  Make sure designs are delivered on time and with the highest quality by using proper checks.

§  Resolve technical issues in developing digital blocks, gate level simulation, power and static timing analysis with team members.

§  Support project managers with effort estimations and resource planning

IV. REQUIREMENTS/ YÊU CẦU

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Education

University and higher

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Major

Electrical and Electronics, Computer science or related majors.

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Experience

10+ years experienced on RTL Design, including technical leadership for a highly complex design.

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Job related requirements

§  Hand-on experience in ISO26262 functional safety related projects, full chip level STA and Power Estimation with PTPX.

§  Very skilled in: Coding using Verilog and SystemVerilog, Synthesis, CDC Verification, Timing Analysis, Equivalence Check.

§  Proficient in C, TCL scripting.

§  Lead the team that performs block design and full-chip level integration.

§  Excellent debugging skills for design issues.

§  Experience in low power/multi voltage design and understanding of UPF is a must.

§  Deep knowledge of Synopsys or Cadence implementation tools and flow.

§  Good team player working with cross cultural and cross functional teams.

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Other requirements

Good communication and interpersonal skills.

Logical thinking

Research and apply new technology

Analytic and troubleshoot problem/

Careful

Ability to multi-task and can work under deadline pressure.

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Gender

Male - Female