CoAsia SEMI (CEO Shin Dong-soo) unveiled its proprietary chiplet-based CoCs™ (CoAsia Chiplet Solution) platform for the first time at 'Arm Unlocked Seoul 2025' on Tuesday, October 21.

'Arm Unlocked Seoul 2025' is a technology leadership summit hosted by the British semiconductor company Arm, designed to share the latest technologies using Arm-based platforms, from cloud to edge, and future industry trends in AI computing. About 500 officials attended, including global tech companies like Samsung, Cadence, and Synopsys, as well as semiconductor partners and industry leaders.

CoAsia SEMI and CoAsia Nexcel, representing CoAsia's system semiconductor division, participated in the event together, jointly introducing the next-generation chiplet platform CoCs™. The presentation was given by CoAsia Nexcel CEO Koh Dae-hyup under the theme 'Driving Chiplet Interoperability: Standards-Based System Design'.

CEO Koh emphasized, "With the rapid spread of AI and High-Performance Computing (HPC), computing performance requirements and systems are becoming more complex. As fine-grained processes to make things smaller advance, the burdens of leakage, heat generation, and cost increase, revealing the limitations of the 'Moore-style expansion' method of simply increasing the density of transistors." He added, "A new alternative is needed that can balance various power and performance requirements."

In this industrial environment, CoAsia SEMI is focusing on enabling customers in the HPC and AI fields to quickly implement SoCs without complex processes, utilizing the Arm Neoverse V3 architecture based on its official Arm Total Design partnership. Furthermore, the company plans to flexibly respond to bridging the gap in the high-performance, low-power competition required in the AI domain by newly proposing its own chiplet architecture platform, 'CoCs™', as an alternative that can reduce costs while enhancing design efficiency and scalability.

CEO Koh explained that 'CoCs™' has a chiplet structure that implements a single system by combining chips (Dies) separated by function, allowing it to be configured by modularizing only the necessary functions. Its strength lies in realizing custom AI/HPC SoCs tailored to customer needs quickly and stably by implementing the server-grade performance and scalability of Arm Neoverse V3 through CoCs™ chiplet modularization, thereby maintaining a balance of Performance, Power, and Area (PPA). This can significantly shorten the time-to-market.

Initial risks were lowered in the design phase by using a pre-verified Compute Sub-System (CSS) utilizing Arm Neoverse V3. In the physical implementation phase, power efficiency was increased and chip area was compressed through an iterative optimization process. Interoperability between each chiplet was also enhanced with a SW Stack for a Standardized Chiplet Interface.

DS Shin (Dong-Soo Shin), CEO of CoAsia SEMI (who also heads the CoAsia Group's Semiconductor Division), stated, "Our company is further strengthening its end-to-end integrated support service for customer-specific chiplet SoCs, covering everything from design to packaging, testing, mass production, and supply chain management." He added, "CoCs™ can effectively respond to interconnect reliability issues and mass production yield management that may occur in a multi-die environment. Through this, we will secure a differentiated competitive edge by reducing our customers' design and development cycles."

Link: 코아시아세미, 'Arm 언락드 서울 2025'서 차세대 칩렛 아키텍처 'CoCs™' 공개